1. Field of the Invention
The invention relates to a clock and data recovery circuit, and more particularly to a clock and data recovery circuit operating at full rate.
2. Description of the Related Art
Generally, compared to a binary clock and data recovery (CDR) circuit, it is easier to analyze and design a linear CDR clock. Moreover, a linear CDR circuit has better performance when considering output phase noise (i.e. less phase noise) and jitter. A conventional linear CDR circuit usually uses a flipflop-based phase detector. However, the flipflop-based phase detector cannot operate at a high rate due to its finite CK-to-Q delay and the time for pulse width comparison.
Recently, with increased electronic device operating rates, CDR circuits are being designed in parallel structures. However, parallel structure designed CDR circuits require additional clock signals. Moreover, parallel structure designed CDR circuits require operation at a half rate or a quarter rate, thus having poorer phase noise performance (i.e. greater phase noise) when compared a CDR circuit operating at a full rate.
Thus, it is desired to provide a CDR circuit which has a linear characteristic and can operate at a high rate.